Project Summary:

The purpose of this project is to gain a theoretical knowledge about FPGA, VGA and do some research on how to use ALTERA DE 2 BOARD also do some research on how to write a coding using Verilog HDL and researcher will expected to display an image in the VGA through ALTERA DE2 board.

Sunday, 19 February 2012

Final Year Project: Week 5

1) Attend briefing/meeting with all FYP students on Tuesday16/2/2012 on 3 pm at TTL 1.The agenda is ;
  • Format of FYP report
2) Block Diagram  of the DE2 Board

  •  All connections are made through the Cyclone II FPGA device. It can configure the FPGA to implement any system design.





 3) Overall Structure of the DE2 Control Panel
  • The DE2 Control Panel facility communicates with a circuit that is instantiated in the Cyclone II FPGA. This circuit is specified in Verilog code, which makes it possible for a knowledgeable user to change the functionality of the Control Panel.Each input/output device is controlled by a controller instantiated in the FPGA chip. The communication with the PC is done via the USB Blaster link. A Command Controller circuit interprets the commands received from the PC and performs the appropriate actions. The SDRAM, SRAM, and Flash Memory controllers have three user-selectable asynchronous ports in addition to the Host port that provides a link with the Command Controller. The connection between the VGA DAC Controller and the FPGA memory allows displaying of the default image shown on the left side of the figure, which is stored in an M4K block in the Cyclone II chip. The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz.The DE2 Control Panel block diagram shown as below:

 








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