Final Year Project: Week 1 and Week 2

Week 1

1.Attend briefing/meeting with all FYP students on Tuesday17/1/2012 on 3 pm at Gemilang Hall.The agenda is ;

• FYP procedure 
• FYP Management

2.Do more research and learn more about Quartus ll software introduction using Verilog  Design starting with general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices, and shows how this flow is realized in the Quartus ll software.  A typical FPGA CAD flow as shown below:

• Design Entry – the desired circuit is specified either by means of a schematic diagram, or  by using a hardware description language, such as Verilog or VHDL

• Synthesis – the entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA chip

• Functional Simulation – the synthesized circuit is tested to verify its functional correctness; this simulation does not take into account any timing issues

• Fitting – the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between specific LEs

• Timing Analysis – propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit

• Timing Simulation – the fitted circuit is tested to verify both its functional correctness and timing

• Programming and Configuration – the designed circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections.

3. Started to use Quartus ll software and do some simple tutorial in this software.

Week 2

  

1.Attend second briefing/meeting with all FYP students on Thursday 26/1/2012 on 3 pm at Gemilang Hall.The agenda is Management of Final Year Project.

2. Continue do some simple tutorial, schematic design circuit in this software and try simulate it. This simple tutorial just to make researcher more familiar with this software. The schematic design and simulation waveform as shown below :